Fundamentals of Parallel Multicore Architecture (Chapman & Hall/CRC Computational Science)

Fundamentals of Parallel Multicore Architecture (Chapman & Hall/CRC Computational Science)

By: Yan Solihin (author)Hardback

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Although multicore is now a mainstream architecture, there are few textbooks that cover parallel multicore architectures. Filling this gap, Fundamentals of Parallel Multicore Architecture provides all the material for a graduate or senior undergraduate course that focuses on the architecture of multicore processors. The book is also useful as a reference for professionals who deal with programming on multicore or designing multicore chips. The text's coverage of fundamental topics prepares students to study research papers in the multicore architecture area. The text offers many pedagogical features, including: Sufficiently short chapters that can be comfortably read over a weekend Introducing each concept by first describing the problem and building intuition that leads to the need for the concept "Did you know?" boxes that present mini case studies, alternative points of view, examples, and other interesting facts or discussion items Thought-provoking interviews with experts who share their perspectives on multicore architectures in the past, present, and future Online programming assignments and solutions that enhance students' understanding The first several chapters address programming issues in shared memory multiprocessors, such as the programming model and techniques to parallelize regular and irregular applications. The core of the book covers the architectures for shared memory multiprocessors. The final chapter contains interviews with experts in parallel multicore architecture.

About Author

Yan Solihin is a professor of electrical and computer engineering at North Carolina State University, where he founded and leads the Architecture Research for Performance, Reliability, and Security (ARPERS) group. Dr. Solihin has been a recipient of the IBM Faculty Partnership Award, NSF Faculty Early Career Award, and AT&T Leadership Award. He is listed in the HPCA Hall of Fame and is a senior member of the IEEE. His research interests include computer architecture, computer system modeling methods, and image processing.


Perspectives on Multicore Architectures The Origin of the Multicore Architecture Perspectives on Parallel Computers Future Multicore Architectures Perspectives on Parallel Programming Limits on Parallel Program Performance Parallel Programming Models Shared Memory Parallel Programming Steps in Parallel Programming Dependence Analysis Identifying Parallel Tasks in Loop Structures Identifying Parallelism at Other Levels Identifying Parallelism through Algorithm Knowledge Determining the Scope of Variables Synchronization Assigning Tasks to Threads Mapping Threads to Processors A Brief Introduction to OpenMP Parallel Programming for Linked Data Structures Parallelization Challenges in LDS Approaches to Parallelization of LDS Parallelization Techniques for Linked Lists The Role of Transactional Memory Introduction to Memory Hierarchy Organization Motivation for Memory Hierarchy Basic Architectures of a Cache Cache Performance Prefetching Cache Design in Multicore Architecture Physical Cache Organization Logical Cache Organization Case Studies Introduction to Shared Memory Multiprocessors The Cache Coherence Problem Memory Consistency Problem Synchronization Problem Basic Cache Coherence Issues Overview Cache Coherence in Bus-Based Multiprocessors Impact of Cache Design on Cache Coherence Performance Performance and Other Practical Issues Broadcast Protocol with Point-to-Point Interconnect Hardware Support for Synchronization Lock Implementations Barrier Implementations Transactional Memory Memory Consistency Models Programmers' Intuition Architecture Mechanisms for Ensuring Sequential Consistency Relaxed Consistency Models Synchronization in Different Memory Consistency Models Advanced Cache Coherence Issues Directory Coherence Protocols Overview of Directory Coherence Protocol Basic Directory Cache Coherence Protocol Implementation Correctness and Performance Contemporary Design Issues Interconnection Network Architecture Link, Channel, and Latency Network Topology Routing Policies and Algorithms Router Architecture Case Study: Alpha 21364 Network Architecture Multicore Design Issues SIMT Architecture SIMT Programming Model Mapping SIMT Workloads to SIMT Cores SIMT Core Architecture Ask the Experts Exercises appear at the end of each chapter.

Product Details

  • ISBN13: 9781482211184
  • Format: Hardback
  • Number Of Pages: 468
  • ID: 9781482211184
  • weight: 1066
  • ISBN10: 1482211181

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