Handbook of 3D Integration, Volume 4: Design, Test, and Thermal Management

Handbook of 3D Integration, Volume 4: Design, Test, and Thermal Management

By: Philip E. Garrou (author), Mitsumasa Koyanagi (author), Eric J. Marinissen (author), Muhannad S. Bakir (author), Paul D. Franzon (author), Peter Ramm (author)Hardback

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This fourth volume of the landmark handbook focuses on the design, testing and thermal management of 3D-integrated devices, both from a technological and a materials science perspective. Edited and authored by key figures from top research institutions and high-tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including the particular challenges and potential. The second part is concerned with the test methods used to assess the quality and reliability of the 3D-integrated devices, while the third and final part deals with thermal management.

About Author

Paul Franzon is Professor in the Department of Electrical and Computer Engineering at North Carolina State University, Raleigh, USA, and director of the Microelectronics Systems Laboratory and co-director of the Electronics Research Laboratory. He received his degrees in physics, mathematics and electrical engineering from the University of Adelaide, Australia, and afterwards moved to the United States to take on a tenure track position at North Carolina State University. Paul Franzon?s teaching and research focuses on building microsystems for applications in computing, communications, sensors, robotics, and signal processing. Erik Jan Marinissen is Principal Scientist at IMEC in Leuven, Belgium. Prior to joining IMEC, he worked at NXP Semiconductors and Philips Research, both in Eindhoven, The Netherlands. He received the MSc degree in computer science and the PhD in software technology from Eindhoven University of Technology. Erik Marinissen?s research interests include all topics in the domain of testing and debugging of integrated circuits. He is a co-author of more than 120 journal and conference papers and a co-inventor of eight granted US and EU patent families. Muhannad S. Bakir is Associate Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, USA. He received the BEng degree from Auburn University, Auburn, AL, in 1999, and the MSc and PhD degrees in electrical and computer engineering from the Georgia Institute of Technology in 2000 and 2003, respectively. His areas of interest include three-dimensional electronic system integration, advanced cooling and power delivery for 3D systems, biosensors and their integration with CMOS circuitry, and nanofabrication technology. Philip Garrou is a consultant and expert witness in the field of IC packaging materials and applications, prior to which he was Director of Technology and Business Development for Dow Chemicals' Electronic Materials business. He is Associate Editor and author of the weekly blog 'Insights from the Leading Edge' for Solid State Technology. Mitsumasa Koyanagi is Professor in the Graduate School of Engineering at Tohoku University, Japan. After his PhD he joined the Central Research Laboratory of Hitachi where he was engaged in the research on semiconductor memories. Afterwards he worked at the Xerox Palo Alto Research Center in California, USA, before he became Professor in the Research Center for Integrated Systems at Hiroshima University, Japan. Peter Ramm is head of the Department for Heterogeneous System Integration at Fraunhofer EMFT in Munich, Germany. After his PhD he worked for Siemens in the DRAM facility where he was responsible for the process integration. In 1988 he joined Fraunhofer IFT (now EMFT) in Munich, focusing for more than 25 years on 3D integration technologies.


PART I: DESIGN 3D Design Styles Design Enablement and Advantages of Ultra-Fine Pitched 3D-Stacked Integrated Circuits Wyoming Case Study IBM Interposers Interposer Interconnect Circuits Signal Integrity for 3D Power Integrity for 3D 2.5D/3D Design Flow Monolithic 3D EDA for 3D 3D Memories 3D Clock Distribution PART II: TEST Cost Modelling for 2.5D and 3D Stacked ICs Interconnect Testing for 2.5D and 3D Stacked ICs Pre-Bond Testing Through Direct Probing of Large-Array Fine-Pitch Micro-Bumps 3D Design-for-Test Architecture Optimization of Test-Access Architectures and Test Scheduling for 3D ICs IEEE P1838 3D Test Access Standard-in-Development Test and Debug Strategy for TSMC CoWoS Stacking Process Based Heterogeneous 3D IC: A Silicon Case Study PART III: THERMAL MANAGEMENT Thermal Challenges and Emerging Solutions for 3D and 2.5D IC Thermal Modeling and Experimental Model Validation for 3D Stacked ICs Thermal Design for 3D ICs with Micro-Fluidics

Product Details

  • ISBN13: 9783527338559
  • Format: Hardback
  • Number Of Pages: 488
  • ID: 9783527338559
  • weight: 1086
  • ISBN10: 3527338551

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