INTEGRATED CIRCUIT DESIGN: GLOBAL EDITI... | WHSmith Books
INTEGRATED CIRCUIT DESIGN: GLOBAL EDITION (4th edition)

INTEGRATED CIRCUIT DESIGN: GLOBAL EDITION (4th edition)

By: Neil Weste (author), David Harris (author)Paperback

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Description

For both introductory and advanced courses in VLSI design, this authoritative, comprehensive textbook is highly accessible to beginners, yet offers unparalleled breadth and depth for more experienced readers. The Fourth Edition of CMOS VLSI Design: A Circuits and Systems perspective presents broad and in-depth coverage of the entire field of modern CMOS VLSI Design. The authors draw upon extensive industry and classroom experience to introduce today's most advanced and effective chip design practices. They present extensively updated coverage of every key element of VLSI design, and illuminate the latest design challenges with 65 nm process examples. This book contains unsurpassed circuit-level coverage, as well as a rich set of problems and worked examples that provide deep practical insight to readers at all levels.

About Author

David Money Harris Associate Professor of Engineering at Harvey Mudd College in Claremont, CA, holds a Ph.D. from Stanford University and S.B. and M.Eng. degrees from MIT. His research interests include CMOS VLSI design, microprocessors, and computer arithmetic. He holds a dozen patents, is the author of three other books in the field of digital design and three hiking guidebooks, and has designed chips at Sun Microsystems, Intel, Hewlett-Packard, and Evans & Sutherland. Neil Weste is a member of the faculty at the Department of Electronic Engineering, Macquarie University; Adjunct Professor of Electrical Engineering at The University of Adelaide; and Director, Engineering at Cisco's Wireless Networking Business Unit. He is a Fellow of the IEEE for his contributions to custom IC design, and a peer elected member of the IEEE Solid State Circuits Society. In 1997 he cofounded Radiata Communications (with David Skellern) which designed the first chip sets for the IEEE 802.11a WLAN standard; in 2001 Radiata was acquired by Cisco. He has served as department head at Bell Laboratories; leader of design projects for Symbolics, Inc.; and as president of TLW, Inc., an IC engineering company that completed groundbreaking chip designs for companies such as North American Philips, Analog Devices, AT&T Microelectronics and Thomson Consumer Electronics.

Contents

Chapter 1 Welcome to VLSI1.1 A Brief History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Preview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3 MOS Transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.4 CMOS Logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.4.1 The Inverter 91.4.2 The NAND Gate 91.4.3 CMOS Logic Gates 91.4.4 The NOR Gate 111.4.5 Compound Gates 111.4.6 Pass Transistors and Transmission Gates 121.4.7 Tristates 141.4.8 Multiplexers 151.4.9 Sequential Circuits 161.5 CMOS Fabrication and Layout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191.5.1 Inverter Cross-Section 191.5.2 Fabrication Process 201.5.3 Layout Design Rules 241.5.4 Gate Layouts 271.5.5 Stick Diagrams 281.6 Design Partitioning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291.6.1 Design Abstractions 301.6.2 Structured Design 311.6.3 Behavioral, Structural, and Physical Domains 311.7 Example: A Simple MIPS Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . 331.7.1 MIPS Architecture 331.7.2 Multicycle MIPS Microarchitectures 341.8 Logic Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381.8.1 Top-Level Interfaces 381.8.2 Block Diagrams 381.8.3 Hierarchy 401.8.4 Hardware Description Languages 401.9 Circuit Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421.10 Physical Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451.10.1 Floorplanning 451.10.2 Standard Cells 481.10.3 Pitch Matching 501.10.4 Slice Plans 501.10.5 Arrays 511.10.6 Area Estimation 511.11 Design Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531.12 Fabrication, Packaging, and Testing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Summary and a Look Ahead 55Exercises 57Chapter 2 Devices2.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612.2 Long-Channel I-V Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642.3 C-V Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682.3.1 Simple MOS Capacitance Models 682.3.2 Detailed MOS Gate Capacitance Model 702.3.3 Detailed MOS Diffusion Capacitance Model 722.4 Nonideal I-V Effects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742.4.1 Mobility Degradation and Velocity Saturation 752.4.2 Channel Length Modulation 782.4.3 Threshold Voltage Effects 792.4.4 Leakage 802.4.5 Temperature Dependence 852.4.6 Geometry Dependence 862.4.7 Summary 862.5 DC Transfer Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872.5.1 Static CMOS Inverter DC Characteristics 882.5.2 Beta Ratio Effects 902.5.3 Noise Margin 912.5.4 Pass Transistor DC Characteristics 922.6 Pitfalls and Fallacies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Summary 94Exercises 95Chapter 3 Speed3.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 993.1.1 Definitions 993.1.2 Timing Optimization 1003.2 Transiet Response ...........................................................................................1013.3 RC Delay Model ...............................................................................................1043.3.1 Effective Resistance 1043.3.2 Gate and Diffusion Capacitance 1053.3.3 Equivalent RC Circuits 1053.3.4 Transient Response 1063.3.5 Elmore Delay 1083.3.6 Layout Dependence of Capcitance 1113.3.7 Determining Effective Resistance 1123.4 Linear Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1133.4.1 Logical Effort 1143.4.2 Parasistic Delay 1143.4.3 Delay in a Logic Gate 1163.4.4 Drive 1173.4.5 Extracting Logical Effort from Datasheets 1173.4.6 Limitations to the Linear Delay Model 1183.5 Logical Effort of Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1213.5.1 Delay in Multistage Logic Networks 1213.5.2 Choosing the Best Number of Stages 1243.5.3 Example 1263.5.4 Summary and Observations 1273.5.5 Limitations of Logical Effort 1293.5.6 Iterative Solutions for Sizing 1293.6 Timing analysis Delay Models. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1313.6.1 Slope-Based Linear Model 1313.6.2 Nonlinear Delay Model 1323.6.3 Current Source Model 1323.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1323.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Summary 134Exercises 134Chapter 4 Power4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1394.1.1 Definitions 1404.1.2 Examples 1424.1.3 Sourches of Power Dissipation 1424.2 Dynamic Power. . . . . . . . . . . . . . . . . . . . . . . 1434.2.1 Activity Factor 1444.2.2. Capacitance 1464.2.3 Voltage 1484.2.4 Frequency 1504.2.5 Short-Circuit Current 1514.2.6 Resonant Circuits 1514.3 Static Powerl . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1524.3.1 Static Power sources 1524.3.2 Power Gating 1554.3.3 Multiple Threshold Voltages and Oxide Thicknesses 1574.3.4 Variable Threshold Voltages 1574.3.5 Input Vector Control 1584.4 Energy-Delay Optimization ...........................................................................1584.4.1 Minimum Energy 1584.4.2 Minimum Energy-Delay Product 1614.4.3 Minimum Energy Under a Delay Constraint 1614.5 Low Power Architectures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1624.5.1 Microarchitecture 1624.5.2 Parallelism and Pipelining 1624.5.3 Power Management Modes 1634.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1644.8 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165Summary 167Exercises 167Chapter 5 Wires5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1695.1.1 Wire Geometry 1695.1.2 Example: Intel Metal Stacks 1705.2 Interconnect Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1715.2.1 Resistance 1725.2.2 Capacitance 1735.2.3 Inductance 1765.2.4 Skin Effect 1775.2.5 Terperature Dependence 1785.3 Interconnect Impact . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1785.3.1 Delay 1785.3.2 Energy 1805.3.3 Crosstalk 1805.3.4 Inductive Effects 1825.3.5 An Aside on Effective Resistance and Elmore Delay 1855.4 Interconnect Engineering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1875.4.1 Width, Spacing and Layer 1875.4.2 Repeaters 1885.4.3 Crosstalk Contol 1905.4.4 Low-Swing Signaling 1925.4.5 Regenerators 1945.5 Logical Effort with Wires. . . . . . . . . . . . . . . . . . . . . . . ...................................1945.6 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195Summary 196Exercises 196Chapter 6 Scaling, Reliability and Variability6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996.2 Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1996.2.1 Supply Voltage 2006.2.2 Termparature 2006.2.3 Process Variation 2016.2.4 Design Corners 2026.3 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2046.3.1 Reliability Terminology 2046.3.2 Oxide Wearout 2056.3.3 Interconnect Wearout 2076.3.4 Soft Errors 2096.3.5 Overvoltage Failure 2106.3.6 Latchup 2116.4 Scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2126.4.1 Transistor Scaling 2136.4.2 Interconnect Scaling 2156.4.3 International Technology Roadmap for Semiconductors 2166.4.4 Impacts on Design 2176.5 Statistical Analysis of Variability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2216.5.1 Properties of Random Variables 2216.5.2 Variation Sources 2246.5.3 Variation Impacts 2276.6 Variation-Tolerant Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2326.6.1 Adaptive Control 2336.6.2 Fault Tolerance 2336.7 Pitfalls and Fallacies ..............................................................................................2356.8 Historical Perspective ............................................................................................236Summary 242Exercises 242Chapter 7 SPICE7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2457.2 A Spice Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2467.2.1 Souirces and Passive Components 2467.2.2 Transistor DC analysis 2507.2.3 Inverter Transient analysis 2507.2.4 Subcircuits and Measurement 2527.2.5 Optimization 2547.2.6 Other HSPICE Commands 2567.3 Device Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2567.3.1 Level 1 Models 2577.3.2 Level 2 and 3 Models 2587.3.3 BSIM Models 2587.3.4 Diffusion Capacitance Models 2587.3.5 Design Corners 2607.4 Device Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2617.4.1 I-V Characteristics 2617.4.2 Threshold Voltage 2647.4.3 Gate Capacitance 2667.4.4 Parasitic Capacitance 2667.4.5 Effective Resistance 2687.4.6 Comparison of Processes 2697.4.7 Process and Environmental Sensitivity 2717.5 Circuit Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2717.5.1 Path Simulations 2717.5.2 DC Transfer Characteristics 2737.5.3 Logical Effort 2737.5.4 Power and Energy 2767.5.5 Simulating Mismatches 2777.5.6 Monte Carlo simulation 2777.6 Interconnect Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2777.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280Summary 282Exercises 282Chapter 8 Gates8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2858.2 Circuit Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2868.2.1 Static CMOS 2878.2.2 Ratioed Circuits 2928.2.3 Cascode Voltage Switch Logic 2978.2.4 Dynamic Circuits 2978.2.5 Pass-Transistor Circuits 3078.3 Circuit Pitfalls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3128.3.1 Threshold Drops 3138.3.2 Ratio Failures 3138.3.3 Leakage 3148.3.4 Charge Sharing 3148.3.5 Power Supply Noise 3148.3.6 Hot Spots 3158.3.7 Minority Carrier Injection 3158.3.8 Back-Gate Coupling8.3.9 Diffusion Input Noise Sensitivity 3168.3.10 Process Sensitivity 3168.3.11 Example: Domino Noise Budgets 3178.4 Silicon-On-Insulator Circuit Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3188.4.1 Floating Body Voltage 3198.4.2 SOI Advantages 3208.4.3 SOI Disadvantages 3208.4.4 Implications for Circuit Styles 3218.4.5 Summary 3228.5 Subthreshold Circuit Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3228.5.1 Sizing 3238.5.2 Gate Selection 3238.6 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3248.7 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325Summary 327Exercises 328Chapter 9 Sequencing9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3339.2 Sequencing Static Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3349.2.1 Sequencing Methods 3349.2.2 Max-Delay Constraints 3379.2.3 Min-Delay Constraints 3419.2.4 Time Borrowing 3449.2.5 Clock Skew 3479.3 Circuit Design of Latches and Flip-Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3499.3.1 Conventional CMOS Latches 3509.3.2 Conventional CMOS Flip-Flops 3519.3.3 Pulsed Latches 3539.3.4 Resettable Latches and Flip-Flops 3549.3.5 Enabled Latches and Flip-Flops 3559.3.6 Incorporating Logic into Latches 3569.3.7 Klass Semidynamic Flip-Flop (SDFF) 3579.3.8 Differential Flip-Flops 3579.3.9 Dual Edge-Triggered Flip-Flops 3589.3.10 Radiation-Hardened Flip-Flops 3599.4 Static Sequencing Element Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3609.4.1 Choice of Elements 3619.4.2 Characterizing Sequencing Element Delays 3639.4.3 State Retention Registers 3669.4.4 Level-Converter Flip-Flops 3669.4.5 Design Margin and Adaptive Sequential Elements 3679.5 Synchronizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ......................................................3699.5.1 Metastability 3709.5.2 A Simple Synchronizer 3739.5.3 Communicating Between Asynchronous Clock Domains 3749.5.4 Common synchronizer Mistakes 3759.5.5 Arbiters 3779.5.6 Degrees of Synchrony 3779.6 Wave Pipelining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3789.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380Summary 381Exercises 383Chapter 10 Datapaths10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38710.2 Addition/Subtraction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38710.2.1 Single-Bit Addition 38810.2.2 Carry-Propagate Addition 39210.2.3 Subtraction 41610.2.4 Multiple-Input Addition 41610.2.5 Flagged Prefix Adders 41710.3 One/Zero Detectors . . . . . . . . . . . . . . . . . . . . . . . . . . . 41910.4 Comparators .............................. . . . . . . . . . . . . . . . . . . . . . . . . . . . 42010.4.1 Magnitude Comparator 42010.4.2 Equality Comparator 42010.4.3 K=A+B Comparator 42110.5 Counters ...................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42110.5.1 Binary Counters 42210.5.2 Fast Binary Counters 42310.5.3 Ring and Johnson Counters 42410.5.4 Linear-Feedback Shift Registers 42410.6 Boolean Logical Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42610.7 Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42610.7.1 Parity 42610.7.2. Error-Correcting Codes 42610.7.3. Gray codes 42810.7.4. XOR/XNOR Circuit Forms 42910.8 Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43010.8.1 Funnel Shifter 43110.8.2 Barrel Shifter 43310.8.3 Alternative Shift Functions 43410.9 Multiplication .................................................................................................. . . . . . 43410.9.1 Unsigned Array Multiplication 43610.9.2 Two's Complement Array Multiplication 43710.9.3 Booth Encoding 43810.9.4 Column Addition 44310.9.5 Final Addition 44710.9.6 Fused Mulitply-Add 44810.9.7 Summary 44810.10 Parallel-Prefix Computations ..........................................................................................44910.11 Pitfalls and Fallacies ......................................................................................................451Summary 452Exercises 452Chapter 11 Memories11.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45511.2 SRAM ...................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45611.2.1 SRAM Cells 45711.2.2 Row Circuitry 46411.2.3 Column Circuitry 46811.2.4 Multi-Ported SRAM and Register Files 47211.2.5 Large SRAMs 47311.2.6 Low-Power SRAMs 47511.2.7 Area, Delay and Power of RAMs and Register Files 47811.3 DRAM ..................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48011.3.1 Subarray Architectures 48111.3.2 Column Circuitry 48311.3.3 EMbedded DRAM 48411.4 Read-Only Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48511.4.1 Programmable ROMs 48711.4.2 NAND ROMs 48811.4.3 Flash 48911.5 Serial Access Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49111.5.1 Shift Registers 49111.5.2 Queues (FIFO, LIFO) 49111.6 Content-Addressable Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49311.7 Programmable Logic Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49511.8 Robust Memory Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49911.8.1 Redundancy 49911.8.2 Error Correcting Codes (ECC) 50111.8.3 Radiation Hardening 50111.9 Historical Perspective . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501Summary 503Exercises 504Chapter 12 Packaging, Power, Clock, I/O12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50712.2 Packaging and Cooling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50712.2.1 Package Options 50712.2.2 Chip-to-Package Connections 50912.2.3 Package Parasitics 51012.2.4 Heat Dissipation 51012.2.5 Temperature Sensors 51112.3 Power Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51312.3.1 On-Chip Power Distribution Network 51412.3.2 IR Drops 51512.3.3 L di/dt Noise 51612.3.4 On-Chip Bypass Capacitance 51712.3.5 Power Network Modeling 51812.3.6 Power Supply Filtering 52212.3.7 Charge Pumps 52212.3.8 Sustrate Noise 52312.3.9 Energy Scavenging 52312.4 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52412.4.1 Definitions 52412.4.2 Clock System Architecture 52612.4.3 Global Clock Generation 52712.4.4. Global Clock Distribution 52912.4.5 Local Clock Gaters 53312.4.6 Clock Skew Budgets 53512.4.7 Adaptive Deskewing 53712.5 PLLs and DLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53812.5.1 PLLs 53812.5.2 DLLs 54512.5.3 Pitfalls 54712.6 I/O.............................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54812.6.1 Basic I/O Pad Circuits 54912.6.2 Electrostatic Discharge Protection 55112.6.3 Example: MOSIS I/O Pads 55212.6.4 Mixed-Voltage I/O 55412.7 High-Speed Links . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55512.7.1 High-Speed I/O channels 55512.7.2. Channel Noise and Interference 55812.7.3 High-Speed Transmitters and Receivers 55912.7.4 Synchronous Data Transmission 56412.7.5 Clock Recovery in Source-Synchronous Systems 56412.7.6 Clock Recoveryin Mesochronous Systems 56612.7.7 Clock Recovery in Pleisochronous Systems 56812.8 Random Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56812.8.1 True Random Number Generators 56812.8.2 Chip Identification 56912.9 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570Summary 571Exercises 572Chapter 13 Methodology13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57313.2 Structured Design Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57513.2.1 A Software Radio-A System Example 57613.2.2 Hierarchy 57813.2.3 Regularity 58113.2.4 Modularity 58313.2.5 Locality 58413.2.6 Summary 58513.3 Design Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58513.3.1 Microprocessor/DSP 58513.3.2 Programmable Logic 58613.3.3 Gate Array and Sea of Gates Design 58913.3.4 Cell-Based Design 59013.3.5 Full Custom Design 59213.3.6 Platform-Based Design-System on a Chip 59313.3.7 Sumary 59413.4 Design Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59413.4.1 Behavioral Synthesis Design flow (ASIC Design Flow) 59513.4.2 Automated Layout Generation 59913.4.3 Mixed-Signal or custom-Design Flow 6013.5 Design Economics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60413.5.1 Non-Recurring Engineering costs (NREs) 60513.5.2 Recurring Costs 60713.5.3 Fixed Costs 60813.5.4 Schedule 60913.5.5 Personpower 61113.5.6 Project Management 61113.5.7 Design Reuse 61213.6 Data Sheets and Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61313.6.1 The Summary 61313.6.2 Pinout 61313.6.3 Description of Operation 61313.6.4 DC Specifications 61313.6.5 AC Specifications 61413.6.6 Package Diagram 61413.6.7 Principles of Operation Manual 61413.6.8 User Manual 61413.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615Exercises 615Chapter 14 Test14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61714.1.1 Logic Verification 61814.1.2 Debugging 62014.1.3 Manufacturing Tests 62214.2 Testers, Test Fixtures and Test Programs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62414.2.1 Testers and Test Fixtures 62414.2.2 Test Programs 62614.2.3 Handlers 62714.3 Logic Verification Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62814.3.1 Test Vectors 62814.3.2 Testbenches and Harnesses 62914.3.3 Regression Testing 62914.3.4 Version Control 63014.3.5 Bug Tracking 63114.4 Silicon Debug Principles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63114.5 Manufacturing Test Principles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63414.5.1 Fault Models 63514.5.2 Observability 63714.5.3 Controllability 63714.5.4 Repeatability 63714.5.5 Survivability 63714.5.6 Fault Coverage 63814.5.7 Automatic Test Pattern Generation (ATPG) 63814.5.8 Delay Fault Testing 63814.6 Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63914.6.1 Ad Hoc Testing 63914.6.2 Scan Design 64014.6.3 Built-In Self-Test (BIST) 64214.6.4 IDDQ Testing 64514.6.5 Design for Manufacturability 64514.7 Boundary Scan..................... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64614.8 Testing in a University Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64714.9 Pitfalls and Fallacies ......................................................................................................648Summary 655Exercices 655Chapter 15 Fabrication15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65715.2 CMOS Technologies . . . . . . . . . . . . . . . . . . . . . . . . . . .................................65815.2.1 Wafer Formation 65815.2.2 Photolithography 65915.2.3 Well and Channel Formation 66115.2.4 Silicon dioxide 66315.2.5 Isolation 66415.2.6 Gate Oxide 66515.2.7 Gate and Source/Drain Formations 66615.2.8 Contacts and Metallization 66815.2.9 Passivation 67015.2.10 Metrology 67015.3 Layout Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67115.3.1 Design Rule Background 67115.3.2 Scribe Line and Other Structures 67415.3.3 MOSIS Scalable CMOS Design Rules 67515.3.4 Micron Design Rules 67615.4 CMOS Process Enhancements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67715.4.1 Transistors 67715.4.2 Interconnect 68015.4.3 Circuit Elements 68215.4.4 Beyond conventional CMOS15.5 Technology-Related CAD Issues ......................................................................68815.5.1 Design Rule Checking (DRC) 68915.5.2 Circuit Extraction 69015.6 Manufacturing Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69115.6.1 Antenna Rules 69115.6.2 Layer Density Rules 69215.6.3 Resolution Enhancement Rules15.6.4 Metal Slotting Rules 69315.6.5 Yield Enhancement Guidelines 69315.7 Pitfalls and Fallacies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69415.8 Historical Perspective ....................................................................................695Summary 697Exercises 697References 699Index 731Credits 751

Product Details

  • ISBN13: 9780321696946
  • Format: Paperback
  • Number Of Pages: 864
  • ID: 9780321696946
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  • ISBN10: 0321696948
  • edition: 4th edition

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