For courses in Hardware Description Languages, Digital Design Laboratory, Digital Design, and Advanced Digital Design. This text focuses on presenting the basic features of the VHDL language in the context of its use for both simulation and synthesis. Basic language concepts are motivated by familiarity with digital logic circuits with simulation and synthesis presented as complementary design processes. Field programmable gate arrays are used as the medium for synthesis laboratory exercises, and tutorials are provided for the use of the new integrated design environments from Xilinx-which is available with the text.
Preface. 1. Introduction. What is VHDL? Digital System Design. The Marketplace. The Role of Hardware Description Languages. Chapter Summary. 2. Modeling Digital Systems. Motivation. Describing Systems. Events, Propagation Delays, and Concurrency. Waveforms and Timing. Signal Values. Shared Signals. Chapter Summary. 3. Simulation vs. Synthesis. The Simulation Model. The Synthesis Model. Field Programmable Gate Arrays (FPGAs). Chapter Summary. 4. Basic Language Concepts: Simulation. Signals. Entity-Architecture. Concurrent Statements. Constructing VHDL Models Using CSAs. Understanding Delays. Chapter Summary. 5. Basic Language Concepts: Synthesis. A Language Directed View of Synthesis. Inference from Declarations. Inference from Simple Concurrent Signal Assignment Statements. Inference from Conditional Signal Assignment Statements. Inference from Selected Signal Assignment Statements. Simulation Behavior vs. Synthesis Behavior. Synthesis Hints. Summary. Exercises. 6. Modeling Behavior: Simulation. The Process Construct. Programming Constructs. More on Processes. The Wait Statement. Attributes. Generating Clocks and Periodic Waveforms. Using Signals in a Process. Modeling State Machines. Constructing VHDL Models Using Processes. Common Programming Errors. Chapter Summary. 7. Modeling Behavior: Synthesis. A Language Directed View of Synthesis. Inference from Within Processes. Miscellaneous Issues. Inference Using Signals vs. Variables. Latch vs. Flip Flop Inference. The Wait Statement. Synthesis of State Machines. Simulation vs., Synthesis Hints. Chapter Summary. 8. Modeling Structure. Describing Structure. Constructing Structural VHDL Models. Hierarchy, Abstraction, and Accuracy. Generics. Component Instantiation and Synthesis. Configurations. Common Programming Errors. Chapter Summary. 9. Subprograms, Packages, and Libraries. Essentials of Functions. Essentials of Procedures. Subprogram and Operator Overloading. Essentials of Packages. Essentials of Libraries. Chapter Summary. 10. Basic Input/Output. Basic Input/Output Operations. The Package TEXTIO. Textbenches in VHDL. ASSERT Statement. A Testbench Template. Chapter Summary. 11. Programming Mechanics. Terminology and Directory Structure. Simulation Mechanics. Synthesis Mechanics. Chapter Summary. 12. Identifiers, Data Types, and Operators. Identifiers. Data Objects. Data Types. Operators. Chapter Summary. References. A. Synthesis Hints. B. VHDL 1987 vs. VHDL 1993. C. Active VHDL Tutorial. D. Xilinx Foundation Express Tutorial. E. Synopsys FPGA Express Tutorial. F. Standard VHDL Packages. G. A Starting Program Template.
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