Lattice Effects in High-Tc Superconductors: Proceedings of the Workshop

Lattice Effects in High-Tc Superconductors: Proceedings of the Workshop

By: T. Egami (editor), etc. (editor), J. Mustre-de Leon (editor), A. Bishop (editor), Yaneer Bar-Yam (editor)Hardback

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The focus of the workshop is the role of crystal lattices, ie atomic structure, phonons, lattice distortions and the mechanism of high temperature superconductivity in oxides. In spite of the intense research effort during the last five years the mechanisms of high temperature superconductivity still remains unknown. While earlier theories focused primarily on the role of magnetic interaction, recent experimental results strongly suggest that anharmonic local atomic displacements are critically involved in creating high temperature superconductivity. In this workshop, experimentalists and theoreticians address this issue with the hope of stimulating real progress in this area.


Part 1 Dependability modelling and evaluation of computing systems: dependable computing - concepts and terminology; dependability modelling and evaluation of hardware-and-software systems; dependability modelling of heterogeneous VAX-cluster systems using stochastic reward nets. Part 2 Fault-tolerant parallel computing systems: communication structures in fault-tolerant distributed systems; present development and future trends in fault testing and tolerance of VLSI; concurrent error detection and reconfiguration in systolic arrays; self-testing of mesh arrays; self-checking bus arbiter and its code for multiprocessing systems; design and reconfiguration strategies for hypertree architectures; yeild evaluation of VLSI reconfigurable binary tree architectures; yield evaluation of tree dynamic RAMs. Part 3 Software fault tolerance in parallel computing systems: new roll-forward checkpointing schemes for modular redundant systems: evaluating the effiency of byzantyne agreement algorithms; optimal strategies for scheduling test and checkpoints; error correction for scheduling test and language. Part 4 Testability design of modules for parallel computing systems: testability design; design for diagnosability-survey; on finding scan flip-flops in partial scan designs; self-checking DCVS circuits; hardware fault detection by diverse software; on t-error correcting and d-unidirectional error detecting codes with d> 1.

Product Details

  • ISBN13: 9789810209704
  • Format: Hardback
  • Number Of Pages: 500
  • ID: 9789810209704
  • ISBN10: 9810209703

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